Fully Integrated Doherty Power Amplifier in CMOS 65nm with Constant PAE in Backoff
Résumé
Design methodology and measurements re-sults are presented for a Doherty Power Amplier fullyintegrated with its input/output network matching andchoke inductances in 65 nm CMOS technology withconstant PAE over a 7 dB backo. Measurements from2.4 GHz to 2.6 GHz show constant PAE performancestarting in 20% level up to 24% with a maximum out-put power of 23.4 dBm. The circuit is fully describedwith all components values and layout details for fur-ther reproduction. Performance graphs showing the ac-tive load-pull eect, sub-ampliers behavior and con-stant PAE prove that it is a real Doherty Power Am-plier with all eects as known by the theory. The cir-cuit is composed by only lumped components, each sub-amplier has cascode topology and their input/outputnetworks are optimized to save die area and to producea constant PAE.