—Synchronization is an issue of significant impor-tance in large-scale, distributed and high-speed systems. Tradi-tional globally synchronous approach is no longer viable due to severe wire delay. Solutions such as "Globally Asynchronous, Lo-cally Synchronous (GALS)" approaches suffer from metastability risk limiting their use in many-core SoC for critical applications, such as aerospace, military or medical equipment. This paper presents a distributed clock generator based on a network of oscillators. A great advantage of this architecture is its high stability and immunity to perturbations. This architecture also makes possible to design large fully synchronous SoC. A 10×10 network supplying clock sources for 100 clock domains has been modeled in VHDL and is under design in silicon. Simulation results show ± 40 ps peak-to-peak phase error between two neighboring clock signals and ± 50 ps between two clocks in distance.