Recently, techniques have been invented to combine encryption and authen- tication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces smaller area compared to two separate algorithms. AE is implemented in the static part of the FPGA (FPGA silicon) in order to secure the recon guration process to ensure the con dentiality and integrity of the bitstream. Also, it is used in the recon gurable part of the FPGA to support applications which need security requirements like Virtual Private Networks (VPNs). This paper presents two di erent directions for implementing AE cores on FPGAs. First, we present e cient ASIC implementations of AE algorithms, Counter with Cipher Block Chaining Mode (CCM) and Galois Counter Mode (GCM), which are used in the static part of the FPGA in order to secure the recon guration process. Our focus on state of the art algorithms for e cient implementations leads to propose e cient compact architectures in order to be used for FPGA bitstream security. Presented ASIC architectures were evaluated by using 90 and 130 nm technologies. Second, high-throughput GCM architectures are implemented in the recon gurable part of the FPGA by taking the advantage of slow changing key environments like VPNs and embedded memory protection. The proposed architectures were evaluated using Virtex5 and Virtex4 FPGAs. It is shown that the performance of the presented work outperforms the previously reported ones.