Area time power estimation for FPGA based designs at a behavioral level
Résumé
A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification.
Mots clés
- behavioral specification
- formal specification
- resource allocation
- area time power estimation
- FPGA based designs
- behavioral level
- performance estimation technique
- power consumption estimation
- Bismuth
- Field programmable gate arrays
- High level synthesis
- Design methodology
- Space technology
- Time factors
- Process design
- Signal processing algorithms
- Array signal processing
- Testing