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Communication Dans Un Congrès Année : 2014

On error models for RTL security evaluations

Résumé

Evaluating early at design time the level of security achieved with respect to fault-based hardware attacks requires understanding and accurately modeling the faults that can actually occur in a circuit under attack. Attacks with lasers can produce single or multiple-bit errors, while having a local impact in the circuit. This paper discusses several fault or error models that can be considered at design time and summarizes experimental results providing some insights into the consequences of the model chosen for evaluation.
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Dates et versions

hal-01010314 , version 1 (19-06-2014)

Identifiants

  • HAL Id : hal-01010314 , version 1

Citer

Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hely, et al.. On error models for RTL security evaluations. 9th Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) 2014, May 2014, Santorini, Greece. pp.1-6. ⟨hal-01010314⟩
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