New methodology design for future generation of Optical Network on Chip "ONoC"
Résumé
With the number of transistors doubling every 18 months, chip designs are moving towards integrating multiple cores on a single chip. Bus-based networks become a bottleneck due to the increase in power consumption and latency with large core counts. Optical interconnection networks have the potential to be a key in communication performance to these future generations of MPSoCs. The use of this type of networks requires the evaluation of design complexity and energy consumption. In this paper, a new design methodology of an optical network on chip using two superposed waveguides levels and a specific optical circuit interface is proposed. Study of network performance and comparison with other realizations demonstrate the potential of the multi-level design paradigm to decrease network complexity and energy consumption.