Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Nuclear Science Année : 2014

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

Résumé

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad. The active area of the circuit is about 0.04 mm2.

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-00983408 , version 1 (25-04-2014)

Identifiants

  • HAL Id : hal-00983408 , version 1

Citer

Yohan Piccin, H. Lapuyade, Yann Deval, Colette Morche, J. -Y. Seyler, et al.. Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology. IEEE Transactions on Nuclear Science, 2014, pp.25-30. ⟨hal-00983408⟩
70 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More