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Communication Dans Un Congrès Année : 2013

Self-aligned contacts for 10nm FDSOI node : from device to circuit evaluation

Résumé

We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optmimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications.
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Dates et versions

hal-00955675 , version 1 (05-03-2014)

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H. Niebojewski, C. Le Royer, Y. Morand, O. Rozeau, M.A. Jaud, et al.. Self-aligned contacts for 10nm FDSOI node : from device to circuit evaluation. 39th IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, IEEE S3S 2013, 2013, Monterey, CA, United States. paper 6a.4, 2 p., ⟨10.1109/S3S.2013.6716549⟩. ⟨hal-00955675⟩
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