RFID ICs such as EPC Class 1 GEN2 tag are low cost tags which are in some cases used for critical or secure applications. Increasing their robustness is not trivial due to the wide range of error sinks (EM perturbations, attacks...). Moreover increasing the robustness must have a minimum impact on the die area but also must fit with a standardized protocol. In this work we propose a design methodology in order to develop hardened digital tag architecture with a dedicated verification environment taking into account all RFID system parameters