Memory testing of an integrated circuit is a real industrial challenge, and presents several interesting original combinatorial opti- mization problems. A simple model for testing a set of memories, tak- ing into account their test time and power, is first presented. Feasible solutions consist on grouping memories into lots of a maximum fixed power. The aim is to minimize the overall test time for a unique sequen- tial tester. The problem includes the classical Bin-Packing problem and thus is N P -hard. A simple lower bound of the overall test time is first obtained using a continuous version of the problem. A simple heuris- tic issued from a Next Fit Decreasing strategy is then presented and its performance ratio is proved to be bounded by 2.