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Enabling the UCD-SPH code on the Xeon Phi


This white-paper reports on our efforts to enable an SPH-based Fortran code on the Intel Xeon Phi. As a result of the work described here , the two most computationally intensive subroutines (rates and shepard_beta) of the UCD-SPH code were refactored and parallelised with OpenMP for the first time, enabling the code to be executed on multi-core and many-core shared memory systems. This parallelisation achieved speedups of up to 4.3x for the rates subroutine and 6.0x for the shepard_beta subroutine resulting in overall speedups of up to 4.2x on a 2 processor Sandy Bridge Xeon E5 machine. The code was subsequently enabled and refactored to execute in different modes on the Intel Xeon Phi co-processor achieving speedups of up to 2.8x for the rates subroutine and up to 3.8x for the shepard_beta subroutine producing overall speedups of up to 2.7x compared to the original unoptimised code. To explore the capabilities of auto-vectorisation the shepard_beta subroutine was refactored which results in speedups of up to 6.4x for the shepard_beta subroutine relative to the original unoptimised version of the shepard_beta subroutine. The development and testing phases of the project were carried out on the PRACE EURORA machine.
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Dates and versions

hal-00927227 , version 1 (12-01-2014)
hal-00927227 , version 2 (22-01-2014)


  • HAL Id : hal-00927227 , version 2


Christian Lalanne, Ashkan Rafiee, Denys Dutykh, Michael Lysaght, Frédéric Dias. Enabling the UCD-SPH code on the Xeon Phi. 2014. ⟨hal-00927227v2⟩
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