Reconfigurable field programmable gate arrays (FPGAs) are employed extensively in many application domains due to their flexibility, high-density functionality and performance. However, the challenge that must be tackled during system design is their high susceptibility to the radiation-induced faults and the physical defects in the circuit due to presence (variability) or appearance (aging). In general, current FPGAs are not designed to work under these error prone environments, except for specific circuits that have been radiation-hardened at the fabrication process level, but at a very high cost overhead, which makes them less interesting from an economic point of view. These issues can be handled by involving proper fault mitigation mechanisms at different levels of FPGA architecture. We then plan to develop a low-cost reliable FPGA with supporting EDA tool-suite that offers a complete environment for a fault tolerant system design. This article presents the proposed ARDyT FPGA architecture. The additional features introduced in this architecture ensures the reliability and increased flexibility in the design.