An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to distribute the Tree-based interconnect netwrok into multiple stacked active silicon layers proposed in this paper.