We describe the design and exploration methodology to optimize 3-dimensional (3D) Heterogeneous Tree-based FPGAs (HT-FPGAs) by introducing a break-point at a particular tree level interconnect to optimize the speed, power consumption and area. The ability of the flow to decide a horizontal or vertical partitioning of the programmable tree network based on design specifications is a defining feature. The break-point of the vertically partitioned tree is designed to balance the placement of logic blocks and switch blocks into multiple tiers while the horizontally partitioned tree is designed to optimize the interconnect delay of the programmable tree network. We finally evaluate the performance, area and power of the proposed 3D HT-FPGA using the newly developed flow and show that vertical and horizontally partitioned 3D stacked HT-FPGA improves speed by 16% and 55% respectively compared to 2D planar design.