As high-speed links become ubiquitous in current networks, testing new algorithms at high-speed is essential for researchers. This task often requires traffic to be generated with some specied features : distribution of packet sizes, payload content, number of TCP or UDP ows... When targeting a data rate of many Gb/s, this cannot be done with commodity computers. Commercial traffic generators exist for this task, but they are expensive and do not t the precise needs of researchers. In this paper, we describe an open-source implementation of a traffic generator capable of lling a 10 Gb/s Ethernet link, with traffic features specied in software. The implementation works on a board including an FPGA and a 10 Gb/s network interface, like the Combo from INVEA-TECH or the NetFPGA 10G. These boards are a ordable for research and can provide a congurable and easily extensible traffic generator.