Hierarchical Enumerative Coding (HENUC) is a lossless compression algorithm used in a wavelet based image encoder. By manipulating the wavelet coefficients into locally stationary sequences, HENUC is demonstrated to provide good compression efficiency according to our experimental results. We extended our previous work on FPGA encoder SoC, exploiting an innovative on-chip memory access manner in the bit-plane coding using dual port, as well as an address-based data traversal technique during the coding. Performance results are based on the Altera's 40nm Stratix IV EP4SGX230 FPGA, on a DE4 board from Terasic, where the optimized dual port HENUC architecture is implemented in a Nios II processor based system on chip. We present the resource utilization and the execution time evaluations. We show that our implementation at 100MHz can provide around 10X speedup over 2.4GHz Intel Xeon 8-core CPU, which is about twice as faster as our previous result.