In the presence of a concrete problem of multi-objective optimization, we are confronting with the principal difficulty to choice a method producing the optimal solutions. This choice implies the knowledge and the expertise of the user. In this framework, we are interested to the flow of design based on methodology AAA (Adequacy Algorithm Architecture). The extension of this methodology to the circuits allows the exploitation of potential parallelism onto components. It aims to obtaining a real time implementation witch respect the temporal constraint of the application while minimizing the resources. Then, from an algorithm specified with a data flow graph, this exploration of parallelism is NP-complete problem. In this work, we propose a new solution to perform a multi-objective exploration by integrating an SVM (Support Vector Machine) training aptitude to an agent. We validate our model by a simulation based on the greedy heuristic results of SynDEX-IC (Synchronized Distributed Executive for Integrated circuit) [1] examples.