Extrinsic base resistance optimization in DPSA-SEG SiGe:C HBTs
Résumé
The influence of an additional annealing in the base/emitter module fabrication of state-of-the-art DPSA-SEG SiGe:C HBTs is studied in this paper. The objective of this annealing is to reduce the extrinsic base resistance R Bx which in previous studies appeared to limit f MAX of DPSA-SEG SiGe HBTs. TCAD simulations and on-silicon measurements are presented for two different base widths. It is shown that the f MAX increase brought by R BX reduction can be traded for a larger f T . A f T /f MAX frequencies couple reaching 320/390 GHz is demonstrated, associated to a CML ring oscillator gate delay time of 2.2 ps.