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Communication Dans Un Congrès Année : 2012

FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and Decoding

Résumé

Hardware prototyping has been the key to system validation, once the hardware simulation matches the software model results and before the final silicon tape-out. On the other hand, flexible multi-standard implementations are being widely investigated these last years for the challenging channel decoding application. The latest contributions explore ASIP (Application-Specific Instruction-set Processor) concept and target to achieve efficient resource sharing between advanced Turbo and LDPC iterative decoders. In this paper we present an FPGA-based prototype of a multi-standard Turbo/LDPC Encoding and Decoding. The functional prototype implements a full communication system including encoder, channel model, ASIP-based decoder and performance counters. All components are flexible and are dynamically configurable through a dedicated GUI (Graphical User Interface). The prototype supports all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.
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Dates et versions

hal-00797561 , version 1 (06-03-2013)

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  • HAL Id : hal-00797561 , version 1

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Purushotham Murugappa Velayuthan, Jean-Noël Bazin, Amer Baghdadi, Michel Jezequel. FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and Decoding. RSP 2012: IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland. ⟨hal-00797561⟩
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