AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Journal of Circuits, Systems, and Computers Année : 2012

AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE

Yousri Ouerhani
  • Fonction : Auteur
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Maher Jridi
Ayman Alfalou

Résumé

In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements (PE). The proposed architecture can perform N-point FFT using only 4/3N delay ele- ments and involves a latency of N/4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has been made to show the efficiency of the proposed design. Moreover, from the experimental results obtained from a FPGA prototype we find that the proposed design involves an execution time of 56% lower than that obtained with Xilinx IP core and an increase of 19% in the throughput by area ratio for 256-point FFT.
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Dates et versions

hal-00782711 , version 1 (31-01-2013)

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  • HAL Id : hal-00782711 , version 1

Citer

Yousri Ouerhani, Maher Jridi, Ayman Alfalou. AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE. Journal of Circuits, Systems, and Computers, 2012, 21 (6), 1240018 (15 p.). ⟨hal-00782711⟩

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