Hardware Discrete Channel Emulator - Archive ouverte HAL
Article Dans Une Revue High Performance Computing and Simulation (HPCS), 2010 International Conference on Année : 2010

Hardware Discrete Channel Emulator

Résumé

In this paper, the emulation environment named Hardware Discrete Channel Emulator (HDCE) has been developed as a coherent framework to emulate on a hardware device (FPGA as the implementation platform in the verification) and simulate on a computer the effect of an Additive White Gaussian Noise (AWGN) in a base band channel. The HDCE is able to generate more than 180 M samples per second for a very low hardware cost, which has been achieved in an efficient architecture. Using the HDCE, the performance evaluation of a coding scheme for a BER of 10−9 requires only one minute of emulation time.
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Dates et versions

hal-00760113 , version 1 (03-12-2012)

Identifiants

Citer

Emmanuel Boutillon, Tang Yangyang, Cédric Marchand, Pierre Bomel. Hardware Discrete Channel Emulator. High Performance Computing and Simulation (HPCS), 2010 International Conference on, 2010, pp.452-458. ⟨10.1109/HPCS.2010.5547099⟩. ⟨hal-00760113⟩
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