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Communication Dans Un Congrès Année : 2012

Equivalent Circuit Synthesis Method for Reduced Order Models of Large Scale Inductive PEEC Circuits

Résumé

This paper describes an original approach for reducing and synthesizing large parasitic RLM electrical circuits coming from inductive PEEC models. The proposed technique enables the re-use of the model in the time domain circuit simulation context.
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Dates et versions

hal-00757554 , version 1 (27-11-2012)

Identifiants

  • HAL Id : hal-00757554 , version 1

Citer

Trung Son Nguyen, Jean-Michel Guichon, Olivier Chadebec, Gérard Meunier. Equivalent Circuit Synthesis Method for Reduced Order Models of Large Scale Inductive PEEC Circuits. CEFC 2012, Nov 2012, Oita, Japan. ⟨hal-00757554⟩
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