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Article Dans Une Revue ACM Transactions on Reconfigurable Technology and Systems (TRETS) Année : 2012

Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance

Jean-Philippe Diguet
Guy Gogniat

Résumé

Asymmetric coherency is a new optimisation method for coherency policies to support non-uniform work- loads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applica- ble to SoC multicores where the applications are not evenly spread among the processors and customization of the coherency is possible. Asymmetric coherency is a policy change, and consequently our designs re- quire little or no additional hardware over an existing system. We explore two different types of asymmetric coherency policies. Our bus based asymmetric coherency policy, generated a 60% coherency cost reduction (reduction of latencies due to coherency messages) for non-shared data. Our directory based asymmetric co- herency policy, showed up to a 5.8% execution time improvement and up to a 22% improvement in average memory latency for the parallel benchmarks Sha, using a statically allocated asymmetry. Dynamically allo- cated asymmetry was found to generate further improvements in access latency, increasing the effectiveness of asymmetric coherency by up to 73.8% when compared to the static asymmetric solution.
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Dates et versions

hal-00747710 , version 1 (01-11-2012)

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  • HAL Id : hal-00747710 , version 1

Citer

John Shield, Jean-Philippe Diguet, Guy Gogniat. Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2012, 5 (3), pp.12. ⟨hal-00747710⟩
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