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Communication Dans Un Congrès Année : 2012

Low Cost 3D Multilevel Interconnect Integration for RF and Microwave Applications

Résumé

This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.
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Dates et versions

hal-00720570 , version 1 (24-07-2012)

Identifiants

  • HAL Id : hal-00720570 , version 1

Citer

Ayad Ghannam, Lamine Ourak, David Bourrier, Christophe Viallon, Thierry Parra. Low Cost 3D Multilevel Interconnect Integration for RF and Microwave Applications. 62nd Electronic Components and Technology Conference (ECTC 2012), May 2012, San Diego, United States. 5p. ⟨hal-00720570⟩
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