<?xml version="1.0" encoding="utf-8"?>
<TEI xmlns="http://www.tei-c.org/ns/1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:hal="http://hal.archives-ouvertes.fr/" xmlns:gml="http://www.opengis.net/gml/3.3/" xmlns:gmlce="http://www.opengis.net/gml/3.3/ce" version="1.1" xsi:schemaLocation="http://www.tei-c.org/ns/1.0 http://api.archives-ouvertes.fr/documents/aofr-sword.xsd">
  <teiHeader>
    <fileDesc>
      <titleStmt>
        <title>HAL TEI export of hal-00685875</title>
      </titleStmt>
      <publicationStmt>
        <distributor>CCSD</distributor>
        <availability status="restricted">
          <licence target="https://creativecommons.org/publicdomain/zero/1.0/">CC0 1.0 - Universal</licence>
        </availability>
        <date when="2026-05-18T20:08:35+02:00"/>
      </publicationStmt>
      <sourceDesc>
        <p part="N">HAL API Platform</p>
      </sourceDesc>
    </fileDesc>
  </teiHeader>
  <text>
    <body>
      <listBibl>
        <biblFull>
          <titleStmt>
            <title xml:lang="en">Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression</title>
            <author role="aut">
              <persName>
                <forename type="first">Maher</forename>
                <surname>Jridi</surname>
              </persName>
              <email type="md5">75f7196576867a96c1afe8c95cb18aca</email>
              <email type="domain">isen.fr</email>
              <idno type="idhal" notation="string">maherjridi</idno>
              <idno type="idhal" notation="numeric">4371</idno>
              <idno type="halauthorid" notation="string">5386-4371</idno>
              <idno type="ORCID">https://orcid.org/0000-0002-9316-7920</idno>
              <idno type="GOOGLE SCHOLAR">https://scholar.google.fr/citations?user=N8Xv4GQAAAAJ&amp;hl=fr</idno>
              <idno type="IDREF">https://www.idref.fr/122168496</idno>
              <affiliation ref="#struct-127868"/>
            </author>
            <author role="aut">
              <persName>
                <forename type="first">Ayman</forename>
                <surname>Alfalou</surname>
              </persName>
              <email type="md5">7a8be394116d22e148bf26d032a37188</email>
              <email type="domain">yncrea.fr</email>
              <idno type="idhal" notation="string">ayman-alfalou</idno>
              <idno type="idhal" notation="numeric">738593</idno>
              <idno type="halauthorid" notation="string">11284-738593</idno>
              <idno type="ORCID">https://orcid.org/0000-0002-3965-4648</idno>
              <idno type="GOOGLE SCHOLAR">https://scholar.google.fr/citations?user=331l9OwAAAAJ&amp;hl=fr</idno>
              <idno type="IDREF">https://www.idref.fr/126887152</idno>
              <idno type="IDREF">https://www.idref.fr/168630907</idno>
              <affiliation ref="#struct-127868"/>
            </author>
            <editor role="depositor">
              <persName>
                <forename>Maher</forename>
                <surname>Jridi</surname>
              </persName>
              <email type="md5">75f7196576867a96c1afe8c95cb18aca</email>
              <email type="domain">isen.fr</email>
            </editor>
          </titleStmt>
          <editionStmt>
            <edition n="v1" type="current">
              <date type="whenSubmitted">2017-05-03 15:59:16</date>
              <date type="whenWritten">2012-02-01</date>
              <date type="whenModified">2026-03-04 12:54:01</date>
              <date type="whenReleased">2017-05-09 10:00:47</date>
              <date type="whenProduced">2010-09-27</date>
              <date type="whenEndEmbargoed">2017-05-03</date>
              <ref type="file" target="https://hal.science/hal-00685875v1/document">
                <date notBefore="2017-05-03"/>
              </ref>
              <ref type="file" subtype="author" n="1" target="https://hal.science/hal-00685875v1/file/978-3-642-28566-0_7_Chapter.pdf" id="file-1517768-1580781">
                <date notBefore="2017-05-03"/>
              </ref>
              <ref type="externalLink" target="https://link.springer.com/content/pdf/10.1007%2F978-3-642-28566-0_7.pdf"/>
            </edition>
            <respStmt>
              <resp>contributor</resp>
              <name key="130046">
                <persName>
                  <forename>Maher</forename>
                  <surname>Jridi</surname>
                </persName>
                <email type="md5">75f7196576867a96c1afe8c95cb18aca</email>
                <email type="domain">isen.fr</email>
              </name>
            </respStmt>
          </editionStmt>
          <publicationStmt>
            <distributor>CCSD</distributor>
            <idno type="halId">hal-00685875</idno>
            <idno type="halUri">https://hal.science/hal-00685875</idno>
            <idno type="halBibtex">jridi:hal-00685875</idno>
            <idno type="halRefHtml">&lt;i&gt;18th International Conference on Very Large Scale Integration (VLSISOC)&lt;/i&gt;, Sep 2010, Madrid, Spain. pp.155-181, &lt;a target="_blank" href="https://dx.doi.org/10.1007/978-3-642-28566-0_7"&gt;&amp;#x27E8;10.1007/978-3-642-28566-0_7&amp;#x27E9;&lt;/a&gt;</idno>
            <idno type="halRef">18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. pp.155-181, &amp;#x27E8;10.1007/978-3-642-28566-0_7&amp;#x27E9;</idno>
            <availability status="restricted">
              <licence target="https://creativecommons.org/licenses/by/4.0/">CC BY 4.0 - Attribution<ref corresp="#file-1517768-1580781"/></licence>
            </availability>
          </publicationStmt>
          <seriesStmt>
            <idno type="stamp" n="IFIP">IFIP - International Federation for Information Processing</idno>
            <idno type="stamp" n="IFIP-AICT" corresp="IFIP">IFIP Advances in Information and Communication Technology</idno>
            <idno type="stamp" n="IFIP-TC" corresp="IFIP">IFIP Technical Committees </idno>
            <idno type="stamp" n="IFIP-WG" corresp="IFIP">Working Groups</idno>
            <idno type="stamp" n="IFIP-VLSISOC" corresp="IFIP">IFIP-VLSISOC</idno>
            <idno type="stamp" n="IFIP-TC10" corresp="IFIP-TC">IFIP-TC10</idno>
            <idno type="stamp" n="IFIP-WG10-5" corresp="IFIP-WG">WG10-5: Design and Engineering of Electronic Systems</idno>
            <idno type="stamp" n="IFIP-AICT-373" corresp="IFIP-AICT">VLSI-SoC: Forward-Looking Trends in IC and Systems Design</idno>
            <idno type="stamp" n="LABISEN">Laboratoire de l'ISEN</idno>
          </seriesStmt>
          <notesStmt>
            <note type="audience" n="2">International</note>
            <note type="invited" n="0">No</note>
            <note type="popular" n="0">No</note>
            <note type="peer" n="1">Yes</note>
            <note type="proceedings" n="1">Yes</note>
          </notesStmt>
          <sourceDesc>
            <biblStruct>
              <analytic>
                <title xml:lang="en">Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression</title>
                <author role="aut">
                  <persName>
                    <forename type="first">Maher</forename>
                    <surname>Jridi</surname>
                  </persName>
                  <email type="md5">75f7196576867a96c1afe8c95cb18aca</email>
                  <email type="domain">isen.fr</email>
                  <idno type="idhal" notation="string">maherjridi</idno>
                  <idno type="idhal" notation="numeric">4371</idno>
                  <idno type="halauthorid" notation="string">5386-4371</idno>
                  <idno type="ORCID">https://orcid.org/0000-0002-9316-7920</idno>
                  <idno type="GOOGLE SCHOLAR">https://scholar.google.fr/citations?user=N8Xv4GQAAAAJ&amp;hl=fr</idno>
                  <idno type="IDREF">https://www.idref.fr/122168496</idno>
                  <affiliation ref="#struct-127868"/>
                </author>
                <author role="aut">
                  <persName>
                    <forename type="first">Ayman</forename>
                    <surname>Alfalou</surname>
                  </persName>
                  <email type="md5">7a8be394116d22e148bf26d032a37188</email>
                  <email type="domain">yncrea.fr</email>
                  <idno type="idhal" notation="string">ayman-alfalou</idno>
                  <idno type="idhal" notation="numeric">738593</idno>
                  <idno type="halauthorid" notation="string">11284-738593</idno>
                  <idno type="ORCID">https://orcid.org/0000-0002-3965-4648</idno>
                  <idno type="GOOGLE SCHOLAR">https://scholar.google.fr/citations?user=331l9OwAAAAJ&amp;hl=fr</idno>
                  <idno type="IDREF">https://www.idref.fr/126887152</idno>
                  <idno type="IDREF">https://www.idref.fr/168630907</idno>
                  <affiliation ref="#struct-127868"/>
                </author>
              </analytic>
              <monogr>
                <title level="m">IFIP Advances in Information and Communication Technology</title>
                <meeting>
                  <title>18th International Conference on Very Large Scale Integration (VLSISOC)</title>
                  <date type="start">2010-09-27</date>
                  <date type="end">2010-09-29</date>
                  <settlement>Madrid</settlement>
                  <country key="ES">Spain</country>
                </meeting>
                <editor>José L. Ayala</editor>
                <editor>David Atienza Alonso</editor>
                <editor>Ricardo Reis</editor>
                <imprint>
                  <publisher>Springer</publisher>
                  <biblScope unit="serie">18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers</biblScope>
                  <biblScope unit="volume">373</biblScope>
                  <biblScope unit="pp">155-181</biblScope>
                  <date type="datePub">2012</date>
                </imprint>
              </monogr>
              <idno type="doi">10.1007/978-3-642-28566-0_7</idno>
            </biblStruct>
          </sourceDesc>
          <profileDesc>
            <langUsage>
              <language ident="en">English</language>
            </langUsage>
            <textClass>
              <keywords scheme="author">
                <term xml:lang="en">Granularity analysis</term>
                <term xml:lang="en">VLSI</term>
                <term xml:lang="en">Digital hard- ware implementation</term>
                <term xml:lang="en">Embedded Image and video compression</term>
                <term xml:lang="en">Canonical Signed Digit</term>
                <term xml:lang="en">Canonical Signed Digit.</term>
                <term xml:lang="en">Multiplierless DCT</term>
              </keywords>
              <classCode scheme="halDomain" n="info.info-ti">Computer Science [cs]/Image Processing [eess.IV]</classCode>
              <classCode scheme="halTypology" n="COMM">Conference papers</classCode>
              <classCode scheme="halOldTypology" n="COMM">Conference papers</classCode>
              <classCode scheme="halTreeTypology" n="COMM">Conference papers</classCode>
            </textClass>
            <abstract xml:lang="en">
              <p>The Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement.</p>
            </abstract>
            <particDesc>
              <org type="consortium">TC 10</org>
              <org type="consortium">WG 10.5</org>
            </particDesc>
          </profileDesc>
        </biblFull>
      </listBibl>
    </body>
    <back>
      <listOrg type="structures">
        <org type="laboratory" xml:id="struct-127868" status="VALID">
          <orgName>Unité de recherche LabISEN</orgName>
          <orgName type="acronym">LabISEN</orgName>
          <desc>
            <address>
              <addrLine>LabISEN – Yncréa Ouest, 20 rue Cuirassé Bretagne, 29200 BREST, FRANCE</addrLine>
              <country key="FR"/>
            </address>
            <ref type="url">https://isen-ouest.fr/</ref>
          </desc>
          <listRelation>
            <relation active="#struct-300066" type="direct"/>
            <relation active="#struct-1053305" type="direct"/>
          </listRelation>
        </org>
        <org type="regroupinstitution" xml:id="struct-300066" status="VALID">
          <orgName>Institut supérieur de l'électronique et du numérique (ISEN)</orgName>
          <desc>
            <address>
              <country key="FR"/>
            </address>
          </desc>
        </org>
        <org type="institution" xml:id="struct-1053305" status="VALID">
          <orgName>YNCREA OUEST</orgName>
          <orgName type="acronym">YO</orgName>
          <desc>
            <address>
              <addrLine>20 rue Cuirassé Bretagne, 29200 BREST, FRANCE</addrLine>
              <country key="FR"/>
            </address>
          </desc>
        </org>
      </listOrg>
    </back>
  </text>
</TEI>