Hardware Transactional Memories (HTM) provide an attractive programming concept which simplifies parallel programs by shifting synchronization problems to the underlying memory system. There has recently been much work in relationship with the implementation of such systems, but to our knowledge, all assume a write-back coherence protocol. As no HTM system is based on a write-through protocol, we propose the design and implementation of a HTM system using a directory based write-through invalidate protocol, and we perform the comparison of this system with a more common HTM system based on a write-back MESI protocol using cycle accurate models. The results indicate that the coherence protocol has an impact on the execution times, but that no solution outperforms the other. However, the write-back protocol shows noticeably better results.