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Communication Dans Un Congrès Année : 2011

Spidergon STNoC design flow

Résumé

In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.
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Dates et versions

hal-00680456 , version 1 (19-03-2012)

Identifiants

  • HAL Id : hal-00680456 , version 1

Citer

F. Dubois, J. Cano, M. Coppola, J. Flich, Frédéric Pétrot. Spidergon STNoC design flow. IEEE/ACM International Symposium on Networks on Chip (NoCS'11), May 2011, Pittsburg, Pa., United States. pp.267 - 268. ⟨hal-00680456⟩

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