Communication Dans Un Congrès Année : 2011

Implementation techniques of high-order FFT into low-cost FPGA

Yousri Ouerhani
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Maher Jridi
Ayman Alfalou

Résumé

In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/area.

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Dates et versions

hal-00671807 , version 1 (18-02-2012)

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Yousri Ouerhani, Maher Jridi, Ayman Alfalou. Implementation techniques of high-order FFT into low-cost FPGA. IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), Sep 2011, Seoul, South Korea. pp.1-4, ⟨10.1109/MWSCAS.2011.6026390⟩. ⟨hal-00671807⟩

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