Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory - Archive ouverte HAL Access content directly
Journal Articles Microelectronics Reliability Year : 2011

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

Abstract

This paper describes a new technique that uses a 1064 nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains.

Dates and versions

hal-00669826 , version 1 (14-02-2012)

Identifiers

Cite

R. Llido, J. Gomez, V. Goubier, N. Froidevaux, L. Dufayard, et al.. Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory. Microelectronics Reliability, 2011, 51, pp.1658-1661. ⟨10.1016/j.microrel.2011.06.050⟩. ⟨hal-00669826⟩
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