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Communication Dans Un Congrès Année : 2011

High-Level Synthesis: On the Path to ESL Design

Philippe Coussy
Cyrille Chavet

Résumé

In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow -a VHDL/Verilog RTL specification, followed by logical and physical synthesis- is no more suitable. Designing MPSoC requires new design approaches raising the specification abstraction up to Electronic System Level (ESL). Hence, virtual prototyping, design space exploration and high-level/system synthesis with the goal of optimised and functionally correct product implementation are needed. In this paper, we present the High-Level Synthesis (HLS) tool named GAUT. From a bit-accurate C/C++ specification and a set of design constraints, GAUT automatically generates a potentially pipelined RTL architecture described in both VHDL and a SystemC respectively used for synthesis and virtual prototyping. Results demonstrate the interest of our approach on a MJPEG application and its capability in exploring various SoC design tradeoffs.
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Dates et versions

hal-00661720 , version 1 (20-01-2012)

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  • HAL Id : hal-00661720 , version 1

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Philippe Coussy, Cyrille Chavet, Dominique Heller. High-Level Synthesis: On the Path to ESL Design. International Conference on ASIC (ASICON 2011), Oct 2011, Xiamen, China. ⟨hal-00661720⟩
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