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Communication Dans Un Congrès Année : 2011

C-elements for hardened self-timed circuits

Résumé

Self-timed circuits are slope sensitive: when the voltage of one input or internal node changes too slowly, the interconnected logical blocks might loose their local one-to-one synchronization. This phenomenon often leads to unwanted global dead-locks of the entire circuit. The deep-submicronic manufacturing process mismatches might create such situations where one logical block is significantly slower than the others. We applied two known solutions for ensuring the correct C-element behavior whatever the slopes are: the transistors are resized and the supply voltage is reduced in order to guarantee the overall chip correctness taking into account the process variations.

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Dates et versions

hal-00652365 , version 1 (15-12-2011)

Identifiants

Citer

F. Ouchet, Katell Morin-Allory, Laurent Fesquet. C-elements for hardened self-timed circuits. 21st International Workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Sep 2011, Madrid, Spain. pp.247-256, ⟨10.1007/978-3-642-24154-3_25⟩. ⟨hal-00652365⟩

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