An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC
Résumé
This paper presents the architecture of an asynchronous digital signal processing chain, working with non-uniformly sampled data in time. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The main advantage of combining the asynchronous design with the non-uniform sampling is the drastic reduction of the power consumption, thanks to the reduction of the computational load.