TurbASIP power consumption analysis and optimization - Archive ouverte HAL
Communication Dans Un Congrès Année : 2010

TurbASIP power consumption analysis and optimization

Résumé

In today’s digital baseband implementation, energy efficiency, flexibility, high performance and low power are major requirements for channel decoding. In this paper we present a detailed power consumption analysis of a flexible ASIP (Application-Specific Instruction-set Processor) for turbo decoding, namely TurbASIP. Based on these analyses, low power techniques are proposed and applied. The optimization techniques show an interesting gain in normalized energy efficiency between 4% and 54% compared to state of the art.
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Dates et versions

hal-00632784 , version 1 (15-10-2011)

Identifiants

  • HAL Id : hal-00632784 , version 1

Citer

Pallavi Reddy, Fabien Clermidy, Rachid Al Khayat, Amer Baghdadi, Michel Jezequel. TurbASIP power consumption analysis and optimization. Colloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2010, Paris, France. ⟨hal-00632784⟩
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