A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders - Archive ouverte HAL
Article Dans Une Revue IEEE Communications Letters Année : 2011

A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders

Résumé

Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.

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Electronique
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Dates et versions

hal-00608287 , version 1 (12-07-2011)

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  • HAL Id : hal-00608287 , version 1

Citer

Ali Al Ghouwayel, Emmanuel Boutillon. A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders. IEEE Communications Letters, 2011, 15 (8), pp 851-853. ⟨hal-00608287⟩
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