CMOS inverter based on Schottky source-drain MOS technology with low-temperature dopant segregation - Archive ouverte HAL
Article Dans Une Revue IEEE Electron Device Letters Année : 2011

CMOS inverter based on Schottky source-drain MOS technology with low-temperature dopant segregation

Résumé

This letter demonstrates the integration of complementary dopant-segregated Schottky barrier MOSFETs into CMOS inverters. The implementation of a valence-band-edge silicide, namely, PtSi, associated to arsenic (As) and boron (B) low-temperature segregation is validated for the first time at the circuit level. Current drives for n- and p-type devices are I on = 596/378 μA/μm at V ds = |1.1 V| and |V gs | = 2 V to account for the 2.4-nm gate oxide thickness. Excellent inverter voltage transfer characteristics, large voltage gain, and appreciable noise margins have been obtained down to 0.5 V of supply voltage.
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Dates et versions

hal-00603004 , version 1 (16-09-2024)

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G. Larrieu, Emmanuel Dubois. CMOS inverter based on Schottky source-drain MOS technology with low-temperature dopant segregation. IEEE Electron Device Letters, 2011, 32 (6), pp.728-730. ⟨10.1109/LED.2011.2131111⟩. ⟨hal-00603004⟩
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