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Communication Dans Un Congrès Année : 2011

Resistance Increase Due to Electromigration Induced Depletion Under TSV

Résumé

3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the best of our knowledge, we propose for the first time an analytical model of resistance increase due to electromigration induced voiding in a line ended by a TSV.

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Dates et versions

hal-00599391 , version 1 (09-06-2011)

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T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, et al.. Resistance Increase Due to Electromigration Induced Depletion Under TSV. IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1 - 3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩. ⟨hal-00599391⟩
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