A new frequency synthesizer stabilization method based on a mixed phase locked loop and delay locked loop
Résumé
A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and a Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of both architectures and in particular to the non-accumulation of random timing jitter in DLL mode. On the other hand, the settling time (less than 0.5µs) of the system is optimized by the increase of the PLL bandwidth, up to instable mode. Multistandard synthesis is so performed within a 1 - 5 GHz range, with a swift agility from one to one.