The interest in using High-Level Synthesis flows to design Digital Signal Processing (DSP) circuits greatly increased in the last years. This is primarily due to the growing processing complexity combined with the limitations of the time-to-market constraint. Dedicated processor design is a complex process, and tools have to optimize processor datapath and controller. In this paper, we propose a controller design flow based on mapping Finite-State Machines into Memory Blocks in order to limit the controller critical path. Our design flow approach takes into account DSP circuit singularities providing efficient area saving compared to other approaches (more than 5%, and up to 62% on real life applications).