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Communication Dans Un Congrès Année : 2010

Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach

Résumé

Parallel hardware architecture proves to be an excellent compromise between area, cost, flexibility and high throughput in the hardware design of LDPC decoder. However, this type of architecture suffers from memory mapping problem: concurrent read and write accesses to data have to be performed at each time instance without any conflict. In this paper, we present an original approach based on the tanner graph modeling and a modified bipartite edge coloring algorithm to design parallel LDPC interleaver architecture.
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Dates et versions

hal-00551432 , version 1 (07-01-2011)

Identifiants

  • HAL Id : hal-00551432 , version 1

Citer

Awais Hussein Sani, Philippe Coussy, Cyrille Chavet, Eric Martin. Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach. IEEE International Conference on Electronics, Circuits, and Systems, Athens, Greece (ICECS) 2010, Dec 2010, Athens, Greece. pp.XX-YY. ⟨hal-00551432⟩
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