A compact model for the drain current and node charges in symmetrical Double-Gate MOSFET, including short-channel and carrier confinement effects is developed. The model is particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical simulation fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current measured in Double-Gate devices fabricated with SON process. Finally, the DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.