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Communication Dans Un Congrès Année : 2010

Modeling of NPN-SiGe-HBT Electrical Performance Improvement through Employing Si3N4 Strain in the Collector Region

Résumé

A new NPN-SiGe-HBT device architecture utilizing a Si3N4 strain layer is proposed. The impact of introducing a Si3N4 strain layer in the collector region on the device's electrical properties and frequency characteristics has been studied using TCAD modeling. An approximately, 8% of improvement in fT, and 5% of improvement in fMAX have been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BVCE0 value (1%─4%), the fT×BVCE0 product enhancement is about 6% by means of strain engineering.

Domaines

Electronique
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Dates et versions

hal-00526042 , version 1 (13-10-2010)

Identifiants

  • HAL Id : hal-00526042 , version 1

Citer

M. Al-Sa'Di, S. Fregonese, C. Maneux, T. Zimmer. Modeling of NPN-SiGe-HBT Electrical Performance Improvement through Employing Si3N4 Strain in the Collector Region. 218th ECS Meeting, Oct 2010, Las Vegas, United States. pp.191-199. ⟨hal-00526042⟩
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