Bit-width Optimization of Extrinsic Informations in Turbo Decoder - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2008

Bit-width Optimization of Extrinsic Informations in Turbo Decoder

Résumé

Soft input soft output (SISO) decoders iteratively exchanging intermediate results (extrinsic information) between themselves lie at the core of turbo decoder architectures. The implementation architecture could be serial, parallel or network on chip (NoC) based. In this paper, we present a technique for bit-width reduction of exchanged extrinsic information and analyze the impact of it for different implementation architectures. The methodology is investigated over two kinds of turbo decoding system, both based on the Max-Log-MAP algorithm. First is a serial concatenated convolutional code (SCCC) decoder and the other is a WiMax (IEEE 802.16e) parallel concatenated convolutional code (PCCC) decoder. For the SCCC decoder, bitwidth of the extrinsic information can be reduced from 8 bits down to 4 without significant bit-error-rate (BER) degradation. For the WiMax case it can be reduced from 8 bits down to 5 with a BER degradation of 0.2 dB.

Mots clés

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-00491635 , version 1 (14-06-2010)

Identifiants

  • HAL Id : hal-00491635 , version 1

Citer

Ashwani Singh, Emmanuel Boutillon, G. Masera. Bit-width Optimization of Extrinsic Informations in Turbo Decoder. 5th International Symposium on Turbo Codes & Related Topics, Sep 2008, Lausanne, Switzerland. pp.134-138. ⟨hal-00491635⟩
112 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More