Upgradeability and interoperability are main concerns of Software Defined Radio (SDR). But in the case of military applications, security is also a relevant aspect of SDR. The Secure Software Communication Architecture (SSCA) is a standardized solution to secure SDR. This architecture needs a cryptographic processor for security purposes. However, currently available SSCA compliant ASIC-based cryptoprocessors limit radio set upgradeability and interoperability. In this paper, we describe the first non-confidential reconfigurable cryptoprocessor architecture for SSCA. We provide some area estimation of processor main parts on Xilinx Virtex 4 FPGA.