Analog-to-Digital (A/D) conversion is faced with strong requirements in terms of resolution and frequency. Time-Interleaved Analog-to-Digital Converters (TIADC) are popular because they offer a higher sampling frequency. But, their architecture introduces errors that affect the resolution of conversion. This paper presents a built-in method of calibration dedicated to TIADC. Mixed-simulations are performed merging transistor-level in 65nm CMOS technology and behavioral blocks in VHDL-AMS language to validate the feasibility of a Built-In Self-Calibration (BISC) system which corrects offset, gain and timing error. Technological constraints of the analog part of the BISC circuitry are highlighted. An orthogonal calibration is applied in a 4-ADC TIADC system and a detailed choice of the methodology is described