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Communication Dans Un Congrès Année : 2010

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Cyrille Chavet
Philippe Coussy
Eric Martin
  • Fonction : Auteur
  • PersonId : 831063
Pascal Urard
  • Fonction : Auteur

Résumé

For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques.
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Dates et versions

hal-00455121 , version 1 (09-02-2010)

Identifiants

Citer

Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. 35th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2010, Mar 2010, Dallas, United States. Pages: 1594-1597, Paper ID : 2559, ⟨10.1109/ICASSP.2010.5495535⟩. ⟨hal-00455121⟩
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