It is currently an acknowledged fact that interconnects introduce delays and consume power and chip resources. To deal with these issues, data coding for interconnect power and timing optimization has been introduced. In today's Systems On Chip, some of these techniques are no longer efficient due to their codec complexity or to their experimentations that are not realistic anymore. Based on some realistic observations on interconnect delay and power estimation, previous works have introduced the Spatial Switching technique, which allows the reduction of delay and power consumption for on-chip buses. This paper deals with some Spatial Switching improvements and also explains how to obtain automatically the best results in terms of power consumption reduction with the Spatial Switching technique by using the Interconnect Explorer tool.