One essential building block for integrated 60 GHz CMOS radio transceivers is the low noise amplifier (LNA). This paper presents a two-stage cascode LNA fabricated in the 65nm bulk CMOS technology of ST Microelectronics. It occupies 0.4mm x 0.4mm die area (pad-limited). For the matching networks, lumped elements are employed exclusively. It can be biased using two different supply voltages: When using 1.5V, a peak gain of 22.4 dB and an output-referred 1 dB compression point of −3.4 dBm is measured while drawing 11.2mA supply current. The simulated noise figure is 4.5 dB. When using a supply voltage of 1.0V, a peak gain of 18.7 dB and an output-referred 1 dB compression point of -6.5 dBm is measured while drawing 8.5mA supply current. The simulated noise figure is 5.2 dB.