As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. This scheduling consists of statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. A static scheduling algorithm is usually described as a monolithic process, and carries out three distinct functions: hoosing the core to execute a specific function, choosing the medium to transfer a specific data block and evaluating the cost of the generated solutions. This paper describes a scheduling framework which splits these functions into reusable sub-modules. This division produces a new level of scalability in terms of schedule quality and computation time, thus enabling the combination of several scheduling heuristics with different architecture models.