Today, System on Chip (SOC) are more and more complex and require many computational resources, implying a large volume of data to be stored or to be transmitted. To transfer this data from memory to processor or from one processor to another, on-chip interconnect buses or networks have to be used. In state-of-the-art SOC, interconnect can represent up to 50% of the total power consumption. Moreover, the transistor and wire dimension scaling has a strong impact on propagation time; indeed the propagation time of a wire is higher than the gate one. Therefore, power and delay estimation and optimization due to interconnections has become a major issue in SOC design. It is thus essential to take interconnect power consumption and delay into account during the first design stages of systems. To do this, we developed a high-level estimation tool (called Interconnect Explorer) which allow user to obtain very fast power and delay estimations of his interconnect network based on both some platform parameters and application data that are handled by the bus.