Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data-coding for interconnect power and timing optimization is a promising method. Based on some realistic observations on interconnect delay and power estimation, a new data-coding technique called ”Convolutional Encoder for Crosstalk Reduction” (CECR) is proposed. It allows the reduction of delay, power consumption (including extra power consumption due to codecs) and noise for on-chip buses. The concept of the technique is to reduce the switching activity to its minimum considering the transmission of data on the encoded wires. Results show the technique efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 10 mm bus in the 65 nm technology and more if buses are longer. It also allows the acceleration of the data propagation of 20% and the reduction of the overall worst noise case transitions of 51%